Current practice involves electrical isolation of the two stacked dies from each other and the leadframe using an electrically insulating die attach material. However, several problems exist when using current practice methods/electrical isolation techniques such as: potential for resin bleeding (contamination of the bond pad near the bottom encapsulant material layer) and contamination of wire bond pads; potential for damage of the lead wires of the lower die during wirebonding of the upper die and during subsequent handling; potential for a lower moisture sensitive level (MSL) because of the larger die attachment interface areas for both the lower and upper dies; a third element is required to create a Z-axis spacing between the two stacked dies by using either a film or a silicon/ceramic spacer; and a leadframe having a large die pad down-set value is needed which may not be manufacturable in high volume.
The moisture sensitive level (MSL) is an important factor to be considered during package design. The MSL determines how long an assembler can keep the parts “on the shelf” before they must be surface mounted on boards. MSL level 1 components are the most desirable and essentially would have an indefinite shelf life. MSL level 2 components have about a one year shelf life and MSL level 3 components only have a one week self life before moisture contamination would render the components unreliable/unusable. Moisture can cause delamination or voids, usually at the chip/die pad interface.
U.S. Pat. No. 6,261,865 B1 to Akram describes a multi-chip semiconductor package using a lead-on-chip lead frame and method of construction.
U.S. Pat. No. 6,087,722 to Lee et al. describes a multi-chip package that does not include a die pad.
U.S. Pat. No. 6,118,176 to Tao et al. describes a stacked chip assembly generally includes a first chip, a second chip and a lead frame.
U.S. Pat. No. 6,297,547 B1 to Akram describes a multiple die package in which a first and second die are mounted on a leadframe.
U.S. Pat. No. 5,814,881 to Alagaratnam et al. describes a stacked integrated chip package and method of making same.
U.S. Pat. No. Re. 36,613 to Ball describes a multiple stacked die device that contains up to four dies and permits close-tolerance stacking by a low-loop-profile wire-bonding operation and a thin-adhesive layer between the stacked dies.
U.S. Pat. No. 6,080,264 to Ball describes an apparatus and method for increasing integrated circuit density comprising utilizing chips with both direct (flip chip type) chip to conductors connection technology and wire bonds and/or tape automated bonding (TAB).
U.S. Pat. No. 6,087,718 to Cho describes a stacked-type semiconductor chip package of a lead-on chip structure which is modified for stacking chips in the package.
U.S. Pat. No. 6,307,257 B1 to Huang et al. describes a dual-chip integrated circuit (IC) package with a chip-die pad formed form leadframe leads.
U.S. Pat. No. 6,337,521 B1 to Masuda describes a semiconductor device and a method of manufacturing the same. The device comprising two semiconductor chips stacked on each other with their backs opposite to each other and sealed with a mold resin.